In the current business environment for integrated circuit device manufacturing, an increasingly used business strategy is for the Integrated Device Manufacturers (IDM's) to go fab-lite or fab-less, and to separate the design and fabrication portions of the manufacturing by sending the fabrication portion of the jobs to dedicated fab companies such as TSMC, UMC, and Chartered.
Whereas the separation of design and fabrication tends to yield an increase in efficiency and lowering of costs, it raises some issues of concern to the manufacturers. The transfer of information between the design houses and the fabrication companies or the failure analysis labs can cause security concerns. This is particularly true when design houses need to transfer design-specific information to the fab or service houses for Failure Analysis (FA) work being done at the fab or service houses.
The basic information required by a fabrication facility in order to fabricate a design is the fabrication level GDS2 files, which show the actual layer-by-layer layout. The GDS2 files yield a local description of the layers, but do not include the descriptions of net names, cell names, or higher level connectivity. The GDS2 files are in binary format, and contain all the layout polygons and their corresponding layer information. Design level files, on the other hand, have different components, as follows:
Library Exchange Format (LEF) files contain building blocks of different Functional Units, e.g., NAND gates, in layout form, and depend on the design rules and the particular fab and technology (i.e., the LEF files are technology-specific). LEF files are normally provided by the fab for each chip. Design files created by the circuit designers are generally created in VHDL or Verilog formats—both ASCII files in high level logic-based languages. Electronic Design Automation (EDA) tools then synthesize, i.e., convert the design files to gate level Net lists in an Electronic Design Interchange Format (EDIF) file. From the EDIF file the EDA tools form Placement And Route (PAR) files which include the actual placement and routing of the Functional Units. From the PAR files, the EDA tools create the fabrication level GDS2 files, which show the actual layer-by-layer layout. The EDA tools can optionally create Design Exchange Format (DEF) files from the PAR files. The DEF files describe how the Functional Unit building blocks are placed and connected by nets, according to the circuit design and design rules. The DEF file is therefore a circuit design in layout format, and includes net connectivity and cell placement. Both the LEF file and the DEF file are in high level ASCII format.
A use of these design and fabrication files in Failure Analysis is described in commonly owned U.S. patent application Ser. No. 11/502,951, filed Aug. 11, 2006, and U.S. Pat. No. 5,675,499, issued Oct. 7, 1997, both of which are hereby incorporated by reference in their entireties. The LEF and DEF files are read by a LEF/DEF Reader, then converted into an efficient, easily accessible cross-mapping database in binary format. When queried by cell or net instance name, the database can provide locations, dimensions and polygons which represent that logical element. Conversely, when queried by physical location, the database can provide cell and/or net instance name corresponding to that location. The cross-mapping database can also be used in conjunction with GDS2 files. The GDS2 files have all the shapes that will be fabricated, in mask layout form. The user can identify these shapes from the GDS2 data. The cross-mapping database has the design element names, plus their corresponding polygons and location. As described in earlier incorporated U.S. patent application Ser. No. 11/502,951, a set of advanced algorithms known as OP3 utilize GDS2 files and the database file to determine optimal placements of probe points, net cuts, and net joins which are utilized in analysis and correction of failures. These determined placements can be indicated on the GDS2 files.
When the aforementioned strategy is used to have the fabrication and failure analysis performed in a special fab facility rather than by the design house, files and data must be transferred to the fab facility from the design facility. The GDS2 files provide the mask data, and are all that are required for the fabrication. However, for failure analysis additional information is generally required, including some cells, nets and/or connectivity data. Currently, the design houses send both the raw GDS2 files or mask data converted into a proprietary format, and additional design information, usually in ASCII format, such as the LEF/DEF, LVS, and/or schematic files. The schematic files are the actual circuit diagrams, which show the complete connectivity of the circuit design, rather than any placement data. The LVS (Layout Vs. Schematic) files check the GDS2 file to be sure it follows the schematic. The design house uses these files as inputs to a layout tool and failure analysis equipment. In this procedure, however, the transfer of the complete design files raises security concerns, and furthermore is not essential, since the FA engineers do not require the full mask data and design information for the FA job.
A method of providing to the fabrication facilities only the information required to perform effective Failure Analysis would alleviate these security concerns when using the fab-lite or fab-less IC manufacturing strategies for design houses.